Although applicable to any high-voltage MOS transistor, the present invention and the problem forming the basis of it are explained with regard to high-voltage MOS transistors in CMOS technology, which are manufactured according to the SVX technique (Smart Voltage Extension).
High-voltage NMOS transistors and high-voltage PMOS transistors, which are manufactured in accordance with SVX technology, are known from IEEE Electron Device Letters, Vol. 21, No. 1, January, 2000, pages 40 to 42, C. Bassin, H. Ballan, and M. Declercq, “High-Voltage Device for 0.5-μm Standard CMOS Technology.” FIG. 4 shows a high-voltage PMOS transistor known from this printed publication.
In FIG. 5, reference numeral 10 denotes a p-doped silicon semiconductor substrate. A deep n-well introduced into semiconductor substrate 10 is denoted by reference numeral 20. A p+-drain region is denoted by reference numeral 30a, and a p-drain extension is denoted by 30b. Reference numeral 40 refers to a p+-doped source region, 50 refers to a gate oxide, 60 refers to a magnetoresistor, which, on one hand, is used as a gate terminal and, on the other hand, is brought onto a LOCOS field-oxide region 70 for controlling the field. Reference numeral 80 denotes an n+-region in the form of an additional well terminal for n-well 20.
The high-voltage PMOS transistor shown in FIG. 5 may be manufactured, using standard 1-μm CMOS technology and 0.5-μm CMOS technology. A corresponding high-voltage NMOS transistor is also described in this printed publication.
Such high-voltage MOS transistors can have avalanche breakdown voltages on the order of 50 Volts at a channel length of <2 μm. If the channel length is selected to be too small, then premature punch-through to the source occurs.
In the case of these known high-voltage transistors, the avalanche breakdown usually occurs in a disadvantageous manner in a region referred to as DB, at which gate oxide 50 and field oxide 70 meet. In particular, this causes the breakdown voltages to be unstable (walk out) and to drift as a function of loading (measuring conditions, wiring) and number of loadings. The change in the breakdown voltage is reversible and may be annealed out.
The main disadvantage of this effect is the lowering of the avalanche breakdown voltage below the value of the p-n junction that is theoretically and physically attainable. In addition, the breakdown voltage shows a strong temperature dependence, which constitutes a considerable disadvantage for applications having a large temperature range.